Enhancement of defect diagnosis based on the analysis of cmos dut behaviour

Tesis doctoral de Daniel Arumi Delgado

Transistor dimensions are scaled down for every new cmos technology. Such high level of integration has increased the complexity of the integrated circuits (ics) manufacturing process, arising new complex failure mechanisms. However, present diagnosis methodologies cannot afford the challenges arisen for future technologies. Furthermore, physical failure analysis, although indispensable, is not feasible on its own, since it requires high cost equipment, tools and qualified personnel. For this reason, a detailed understanding and knowledge of defect behaviours is a key factor for the development of improved diagnosed methodologies to overcome the challenges of nanometer technologies. In this context, this thesis presents the analysis of existing and new failure mechanisms and proposed new diagnosis methodologies to improve the diagnosis of faults, focused on bridging and open faults. iddq is a well known technique for the diagnosis of bridging faults. However, previous works have not considered the impact of the downstream current for the diagnosis of such faults. In this thesis, the impact and the dependence of the downstream current with the power supply voltage (vdd) is analyzed and experimentally measured. Furthermore, a multiple level iddq based diagnosis technique is presented. This method takes benefit from the currents generated by the different network excitations. This technique is successfully applied to real defective devices from 0.18 µm and 90 nm technologies. as an alternative to current based techniques, shmoo plots can be also useful for diagnosis purposes. Low voltage has been traditionally considered as an advantageous condition for the detection of bridging faults. However, it is demonstrated that in presence of bridges connecting balanced n- and p-networks, high vdd values are also advantageous for the detection of bridges, which has its direct translation into diagnosis application. Experimental evidence of this fact is presented. related to open faults, an experimental chip has been designed and fabricated in a 0.35 µm technology, where full and resistive open defects have been intentionally added. Different experiments have been carried out so that the impact of the neighbouring coupling capacitances has been quantified. Furthermore, for resistive opens, experiments have demonstrated the influence of the history effect and the location of the defect on the delay. Traditionally, it has been reported that the highest delay is obtained when the resistive open is located at the beginning of the net. Nevertheless, this thesis demonstrates that this is not true for low resistive open, since the highest delay is obtained for an intermediate location. Experimental measurements prove this behaviour. derived from the results obtained with the fabricated chip, a new methodology for the diagnosis of interconnect full open defects is developed. The fos (full open segment) method divides the interconnect line into different segments based on the topology of the faulty line. Knowing the logic state of the neighbouring lines, the floating net voltage is predicted and compared with the experimental results obtained on the tester. This method has been successfully applied to a set of 0.18 µm defective devices. finally, the impact of the gate tunnelling leakage currents on the behaviour of full open defects has also been analyzed. As technology dimensions are scaled down, the oxide thickness is thin enough so that the gate tunnelling leakage currents influence the behaviour of floating lines. They cause transient evolutions on the floating node until reaching the steady state, which is technology dependent. It is experimentally demonstrated that these evolutions are in the order of seconds for a 0.18µm technology. However, for future technologies, simulations show that the evolutions decrease down to a few µs. Based on this factor, some full open faults present in 0.18 µm technology devices are diagnosed.

 

Datos académicos de la tesis doctoral «Enhancement of defect diagnosis based on the analysis of cmos dut behaviour«

  • Título de la tesis:  Enhancement of defect diagnosis based on the analysis of cmos dut behaviour
  • Autor:  Daniel Arumi Delgado
  • Universidad:  Politécnica de catalunya
  • Fecha de lectura de la tesis:  11/07/2008

 

Dirección y tribunal

  • Director de la tesis
    • Rosa Rodríguez Montañés
  • Tribunal
    • Presidente del tribunal: joan Figueras pí mies
    • michel Renovell (vocal)
    • victor hugo Champac vilela (vocal)
    • camelia Hora (vocal)

 

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