Tesis doctoral de Antonio Portero Trujillo
The main goal of this thesis is to obtain a set of results for the implementation of a given system level application down to different architectural platforms. This allowed carrying out a fair comparison that includes to build the whole system and to complete the design chain to the diverse silicon targets. This comparison uses four variables for its evaluation (execution time, chip area, energy consumption and design time) and produces a map of different optimal implementation points according to a given set or operating requirements. I built a complete mpeg-4 mp. This standard is a well known reference example, pretty popular in the scientific literature and this compressor is also a fine example of data-flow application. Therefore, results extracted from this thesis can be extended to other data-flow applications. I considered necessary to compute image compression with real-time constraints. Hence, i would like to dispose of the most flexible design possible in order to map the same specification into the different platforms. for that purpose, i chose systemc/c++ as description system level language and setup the different implementation flows for the different architectural and silicon platforms. This powerful framework allows comparing implementations in a reasonably objective way. Since our results come from a unique reference model and all designs were finally mapped in the same silicon technology (90nm cmos). the result of this research work is a set of criteria and a map of the available solutions on the performance space rather than an assertion saying that a unique solution is better than others. My intention has been to develop techniques and formulate methods that increased design productivity. This development can be further applied to the new parading of implementations: those that use dvfs techniques and noc-based mpsoc implementation explorations. thesis contributions can be divided in 2 types: quantitative and qualitative contributions: we consider the most significant quantitative contribution is the development of the model able to achieve the different experiments: the mpeg compressor that has been realized in systemc/c ++. It is designed in a way that multiple implementations are possible, ranging from a large part in hw up to loaded in an accelerator as a vliw. In case of the fpga and asic, two implementations have been carried out. We obtained a set of values for seven different implementations targeting four different hw platforms (fpga, asic, dsp and asip) with diverse internal architectures, selected to get optimal points. In the case of asic, we managed to end up with the layouts of the two solutions. This led to an increase in efficiency of 56 % for speed versus 26 % for energy (in fsme solution 20% for speed and 57% for energy in fast solution). In case of the isps, code improvements have been accomplished to come up to more ideal solutions with regard to those who would be obtained by a direct implementation. In case of the asip the improvements have not only been realized in the code but also in the silicon micro architecture that form the vliw. Other qualitative contribution is the accomplishment of a functional noc in systemc.
Datos académicos de la tesis doctoral «Design space exploration of heterogeneous soc platform for a data-dominant application«
- Título de la tesis: Design space exploration of heterogeneous soc platform for a data-dominant application
- Autor: Antonio Portero Trujillo
- Universidad: Autónoma de barcelona
- Fecha de lectura de la tesis: 26/06/2009
Dirección y tribunal
- Director de la tesis
- Jordi Carrabina Bordoll
- Tribunal
- Presidente del tribunal: lluís Terés terés
- francky Catthoor (vocal)
- (vocal)
- (vocal)