Adaptive memory hierarchies for next generation tiled microarchitectures

Tesis doctoral de Enric Herrero Abellanas

Processor performance and memory performance have improved at different rates during the last decades, limiting processor performance and creating the well known «memory gap». Solving this performance difference is an important research field and new solutions must be proposed in order to have better processors in the future. Several solutions exist, such as caches, that reduce the impact of longer memory accesses and conform the system memory hierarchy. However, most of the existing memory hierarchy organizations were designed for single processors or traditional multiprocessors. Nowadays, the increasing number of available transistors has allowed the apparition of chip multiprocessors, which have different constraints and require new ad-hoc memory systems able to efficiently manage memory resources. Therefore, in this thesis we have focused on improving the performance and energy efficiency of the memory hierarchy of chip multiprocessors, ranging from caches to dram memories. in the first part of this thesis we have studied traditional cache organizations such as shared or private caches and we have seen that they behave well only for some applications and that an adaptive system would be desirable. State-of-the-art techniques such as cooperative caching (cc) take advantage of the benefits of both worlds. This technique, however, requires the usage of a centralized coherence structure and has a high energy consumption. Therefore we propose the distributed cooperative caching (dcc), a mechanism to provide coherence to chip multiprocessors and apply the concept of cooperative caching in a distributed way. Through the usage of distributed directories we obtain a more scalable solution and, in addition, has a more flexible and energy-efficient tag allocation method. we also show that applications make different uses of cache and that an efficient allocation can take advantage of unused resources. We propose elastic cooperative caching (elasticcc), an adaptive cache organization able to redistribute cache resources dynamically depending on application requirements. One of the most important contributions of this technique is that adaptivity is fully managed by hardware and that all repartitioning mechanisms are based on distributed structures, allowing a better scalability. Elasticcc not only is able to repartition cache sizes to application requirements, but also is able to dynamically adapt to the different execution phases of each thread. Our experimental evaluation also has shown that the cache partitioning provided by elasticcc is efficient and is almost able to match the off-chip miss rate of a configuration that doubles the cache space. finally, we focus in the behavior of dram memories and memory controllers in chip multiprocessors. Although traditional memory schedulers work well for uniprocessors, we show that new access patterns advocate for a redesign of some parts of dram memories. Several organizations exist for multiprocessor dram schedulers, however, all of them must trade-off between memory throughput and fairness. We propose thread row buffers, an extended storage area in dram memories able to store a data row for each thread. This mechanism enables a fair memory access scheduling without hurting memory throughput. overall, in this thesis we present new organizations for the memory hierarchy of chip multiprocessors which focus on the scalability and of the proposed structures and adaptivity to application behavior. Results show that the presented techniques provide a better performance and energy-efficiency than existing state-of-the-art solutions.

 

Datos académicos de la tesis doctoral «Adaptive memory hierarchies for next generation tiled microarchitectures«

  • Título de la tesis:  Adaptive memory hierarchies for next generation tiled microarchitectures
  • Autor:  Enric Herrero Abellanas
  • Universidad:  Politécnica de catalunya
  • Fecha de lectura de la tesis:  05/07/2011

 

Dirección y tribunal

  • Director de la tesis
    • Ramón Canal Corretger
  • Tribunal
    • Presidente del tribunal: Antonio Gonzalez colas
    • yiannakis Sazeides (vocal)
    • david Kaeli (vocal)
    • pedro Marcuello pascual (vocal)

 

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