Architectural support for high-performing hardware transactional memory systems

Tesis doctoral de Marc Lupon Navazo

Transactional memory ™ has emerged as a promising programming model that solves the tradeoff between high performance and ease of use. In tm, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of tm environments, hardware tm (htm) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. existing htm systems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most htm implementations are «adhoc» and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost htm systems that yield good performance for any kind of tm program. our first contribution, fastm, introduces a novel mechanism to elegantly manages speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach slightly modifies the coherence controller engine to keep in private caches those values generated by in-flight transactions and moves to shared caches the old state. Thus, fastm allows permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place memory updates. Thus fastm is not hurt from capacity issues nor slows down when it has to undo transactional modifications. our second contribution includes two different htm systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces complexity of the system with respect to previous proposals. The first one, fusetm, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, fusetm brings fast transactional computation without requiring neither additional hardware nor extra communication at the end of speculative execution. The second one, spectm, introduces a two-level data versioning mechanism to resolve conflicts in a deferred fashion even in the case of overflow. our third and last contribution presents a couple of truly flexible htm systems that can dynamically adapt their underlying mechanisms accordingly the characteristics of the program. Dyntm records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. Swaptm takes a different approach: it tracks information of the current transactional instance to change its priority level at run-time. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes.

 

Datos académicos de la tesis doctoral «Architectural support for high-performing hardware transactional memory systems«

  • Título de la tesis:  Architectural support for high-performing hardware transactional memory systems
  • Autor:  Marc Lupon Navazo
  • Universidad:  Politécnica de catalunya
  • Fecha de lectura de la tesis:  23/12/2011

 

Dirección y tribunal

  • Director de la tesis
    • Grigorios Magklis
  • Tribunal
    • Presidente del tribunal: josep Torrellas jovani
    • Manuel eugenio Acacio sanchez (vocal)
    • joan manel Parcerisa bundó (vocal)
    • Emilio Lopez zapata (vocal)

 

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